-- C16 System On Chip Architecture
-- Copyright (C) 2003 by Cole Design and Development all rights reserved

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;

entity timer is
    Port (
	 	enable : in std_logic;								-- rtc enable
  		clock : in std_logic;								-- clock signal
		reset : in std_logic;								-- reset input
		cs : in std_logic;									-- chip select
		read : in std_logic;									-- read data
		write : in std_logic;								-- write data
		data_in : in std_logic_vector (15 downto 0);	-- bytes read
		data_out : out std_logic_vector (15 downto 0);-- bytes written
		clock_sec : out std_logic);						-- 1 Hz timer tick
end timer;

architecture Behavioral of timer is
   signal count_clock: unsigned (5 downto 0);
   signal count_u_sec: unsigned (9 downto 0);
   signal count_m_sec: unsigned (9 downto 0);

begin

	process(enable, cs, read)
	begin
		if enable = '1' and cs = '1' and read = '1' then
--			data_out <= "000000" & std_logic_vector(count_m_sec); -- temporary
			data_out <= "0000000000000001"; -- temporary
		else
			data_out <= "ZZZZZZZZZZZZZZZZ";
		end if;
	end process;

	process(count_m_sec)
	begin
		if (count_m_sec < 500) then
			clock_sec <= '1';
		else
			clock_sec <= '0';
		end if;
	end process;

	process(clock, reset)
	begin
		if rising_edge(clock) then
			if reset = '1' or enable = '0' then
				count_clock <= "000000";
				count_u_sec <= "0000000000";
				count_m_sec <= "0000000000";
			elsif count_clock < 49 then
				count_clock <= count_clock + 1;
			else
				count_clock <= "000000";
				if (count_u_sec < 999) then
					count_u_sec <= count_u_sec + 1;
				else
					count_u_sec <= "0000000000";
					if (count_m_sec < 999) then
						count_m_sec <= count_m_sec + 1;
					else
						count_m_sec <= "0000000000";
					end if;
				end if;
			end if;
		end if;
	end process;

end Behavioral;