-- C16 System On Chip Architecture -- Copyright (C) 2003 by Cole Design and Development all rights reserved library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.all; entity rtc is Port ( enable : in std_logic; -- rtc enable clock_sec : in std_logic; -- 1 Hz timer tick reset : in std_logic; -- reset input cs : in std_logic; -- chip select read : in std_logic; -- read data write : in std_logic; -- write data data_in : in std_logic_vector (15 downto 0); -- bytes read data_out : out std_logic_vector (15 downto 0)); -- bytes written end rtc; architecture Behavioral of rtc is signal count_sec: unsigned(5 downto 0); -- seconds signal count_min: unsigned(5 downto 0); -- minutes signal count_hr: unsigned(4 downto 0); -- hours signal count_day: unsigned(4 downto 0); -- days (TODO: always assumes 30 days) signal count_month: unsigned(3 downto 0); -- months signal count_year: unsigned(15 downto 0); -- years begin process(enable, cs, read, count_sec) begin if read = '1' and cs = '1' and enable = '1' then data_out <= "0000000000" & std_logic_vector(count_sec); else data_out <= "ZZZZZZZZZZZZZZZZ"; end if; end process; process(clock_sec, reset, enable) begin if reset = '1' or enable = '0' then count_sec <= "000000"; count_min <= "000000"; count_hr <= "00000"; count_day <= "00000"; count_month <= "0000"; count_year <= "0000000000000000"; elsif rising_edge(clock_sec) then if count_sec < 59 then count_sec <= count_sec + "000001"; else count_sec <= "000000"; if (count_min < 59) then count_min <= count_min + "000001"; else count_min <= "000000"; if (count_hr < 23) then count_hr <= count_hr + "00001"; else count_hr <= "00000"; -- TODO: real month lengths, not just 30 if (count_day < 29) then count_day <= count_day + "00001"; else count_day <= "00000"; if (count_month < 11) then count_month <= count_month + "0001"; else count_month <= "0000"; count_year <= count_year + "0000000000000001"; end if; end if; end if; end if; end if; end if; end process; end Behavioral;